Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CY7C64315-16LKXC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C64315-16LKXC
Description  enCoRe??V Full Speed USB Controller
Download  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C64315-16LKXC Datasheet(HTML) 5 Page - Cypress Semiconductor

  CY7C64315-16LKXC Datasheet HTML 1Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 2Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 3Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 4Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 5Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 6Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 7Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 8Page - Cypress Semiconductor CY7C64315-16LKXC Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 40 page
background image
CY7C6431x
CY7C6434x
CY7C6435x
Document Number: 001-12394 Rev. *P
Page 5 of 40
SPI configuration register (SPI_CFG) sets master/slave
functionality, clock speed, and interrupt select. SPI control
register (SPI_CR) provides four control bits and four status bits
for device interfacing and synchronization.
The SPIM hardware has no support for driving the Slave Select
(SS_) signal. The behavior and use of this signal is dependent
on the application and enCoRe V device and, if required, must
be implemented in firmware.
There is an additional data input in the SPIS, Slave Select (SS_),
which is an active low signal. SS_ must be asserted to enable
the SPIS to receive and transmit. SS_ has two high level
functions:
To allow for the selection of a given slave in a multi-slave
environment.
To provide additional clocking for TX data queuing in SPI modes
0 and 1.
I2C Slave
The I2C slave enhanced communications block is a
serial-to-parallel processor, designed to interface the enCoRe V
device to a two-wire I2C serial communications bus. To eliminate
the need for excessive CPU intervention and overhead, the block
provides I2C-specific support for status detection and generation
of framing bits. By default, the I2C slave enhanced module is
firmware compatible with the previous generation of I2C slave
functionality. However, this module provides new features that
are configurable to implement significant flexibility for both
internal and external interfacing. The basic I2C features include:
Slave, transmitter, and receiver operation.
Byte processing for low CPU overhead.
Interrupt or polling CPU interface.
Support for clock rates of up to 400 kHz.
7- or 10-bit addressing (through firmware support).
SMBus operation (through firmware support).
Enhanced features of the I2C Slave Enhanced Module include:
Support for 7-bit hardware address compare.
Flexible data buffering schemes.
A "no bus stalling" operating mode.
A low power bus monitoring mode.
The I2C block controls the data (SDA) and the clock (SCL) to the
external I2C interface through direct connections to two
dedicated GPIO pins. When I2C is enabled, these GPIO pins are
not available for general purpose use. The enCoRe V CPU
firmware interacts with the block through I/O register reads and
writes, and firmware synchronization is implemented through
polling and/or interrupts.
In the default operating mode, which is firmware compatible with
previous versions of I2C slave modules, the I2C bus is stalled
upon every received address or byte, and the CPU is required to
read the data or supply data as required before the I2C bus
continues. However, this I2C Slave Enhanced module provides
new data buffering capability as an enhanced feature. In the
EZI2C buffering mode, the I2C slave interface appears as a
32-byte RAM buffer to the external I2C master. Using a simple
predefined protocol, the master controls the read and write
pointers into the RAM. When this method is enabled, the slave
never stalls the bus. In this protocol, the data available in the
RAM (this is managed by the CPU) is valid.
Figure 5. I2C Block Diagram
I2C Core
I2C Basic
Configuration
I2C_CFG
I2C_SCR
I2C_DR
Plus Features
HW Addr Cmp
Buffer Module
CPU Port
Buffer Ctl
32 Byte RAM
I2C Plus
Slave
I2C_ADDR
SDA_OUT
SCL_IN
SYSCLK
I2C_EN
To/From
GPIO
Pins
STANDBY
SCL_OUT
SDA_IN
I2C_XSTAT
I2C_XCFG
I2C_BUF
I2C_BP
I2C_CP
MCU_CP
MCU_BP


Similar Part No. - CY7C64315-16LKXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C64315-16LKXC CYPRESS-CY7C64315-16LKXC Datasheet
634Kb / 26P
   enCoRe??V Full-Speed USB Controller
CY7C64315-16LKXC CYPRESS-CY7C64315-16LKXC Datasheet
806Kb / 29P
   enCoRe??V Full-Speed USB Controller
CY7C64315-16LKXC CYPRESS-CY7C64315-16LKXC Datasheet
711Kb / 28P
   enCoRe V Full Speed USB Controller
CY7C64315-16LKXC CYPRESS-CY7C64315-16LKXC Datasheet
928Kb / 32P
   enCoRe V Full Speed USB Controller
CY7C64315-16LKXC CYPRESS-CY7C64315-16LKXC Datasheet
1Mb / 37P
   enCoRe V Full Speed USB Controller
More results

Similar Description - CY7C64315-16LKXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C6431X CYPRESS-CY7C6431X_11 Datasheet
1Mb / 37P
   enCoRe V Full Speed USB Controller
CY7C6431X_09 CYPRESS-CY7C6431X_09_09 Datasheet
928Kb / 32P
   enCoRe V Full Speed USB Controller
CY7C6435X CYPRESS-CY7C6435X Datasheet
634Kb / 26P
   enCoRe??V Full-Speed USB Controller
CY7C6431X CYPRESS-CY7C6431X Datasheet
806Kb / 29P
   enCoRe??V Full-Speed USB Controller
CY7C6431X CYPRESS-CY7C6431X_09 Datasheet
711Kb / 28P
   enCoRe V Full Speed USB Controller
CY7C64215 CYPRESS-CY7C64215 Datasheet
637Kb / 26P
   enCoRe??III Full Speed USB Controller
CY7C64215 CYPRESS-CY7C64215_08 Datasheet
953Kb / 30P
   enCoRe??III Full Speed USB Controller
CY7C63221A CYPRESS-CY7C63221A Datasheet
960Kb / 49P
   enCoRe USB Low-speed USB Peripheral Controller
CY7C63310 CYPRESS-CY7C63310 Datasheet
1Mb / 83P
   enCoRe??II Low-Speed USB Peripheral Controller
CY7C63310 CYPRESS-CY7C63310_12 Datasheet
1,018Kb / 91P
   enCoRe??II Low Speed USB Peripheral Controller
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com