CY7C25652KV18-400BZXC datasheet(11/31 Pages) CYPRESS

Part #	CY7C25652KV18-400BZXC

Description	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C25632KV18

CY7C25652KV18

Document Number: 001-66482 Rev. *D

Page 11 of 31

Write Cycle Descriptions

The write cycle description table for CY7C25652KV18 follows. [14, 15]

BWS0 BWS1 BWS2 BWS3

K

Comments

L

L–H

–

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L

–

L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L

H

L–H

–

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

L

H

–

L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

H

L

H

L–H

–

During the data portion of a write sequence, only the byte (D[17:9]) is written into the

device. D[8:0] and D[35:18] remains unaltered.

H

L

H

–

L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the

device. D[8:0] and D[35:18] remains unaltered.

H

L

H

L–H

–

During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

L

H

–

L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

L

L–H

–

During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H

L

–

L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H

L–H

–

No data is written into the device during this portion of a write operation.

H

–

L–H No data is written into the device during this portion of a write operation.

Note

14. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

represents rising edge.

15. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions

of a write cycle, as long as the setup and hold requirements are achieved.

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