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AD9779BSVZ Datasheet(PDF) 6 Page - Analog Devices |
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AD9779BSVZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 56 page AD9776/AD9778/AD9779 Rev. A | Page 6 of 56 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. S OUTF I Table 2. AD9776, AD9778, and AD9779 Digital Specifications Parameter Conditions Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 2.0 V Input VIN Logic Low 0.8 V Maximum Input Data Rate at Interpolation 1× 300 MSPS 2× 250 MSPS 4× 200 MSPS 8× 125 MSPS CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1 Output VOUT Logic High 2.4 V Output VOUT Logic Low 0.4 V LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN2 80 120 Ω LVDS Input Rate 125 MSPS Set-Up Time, SYNC_I to DAC Clock −0.2 ns Hold Time, SYNC_I to DAC Clock 1 ns LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Output Voltage High, VOA or VOB 825 1575 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, RO Single-ended 80 100 120 Ω Maximum Clock Rate 1 GHz DAC CLOCK INPUT (CLK+, CLK−) Differential Peak-to-Peak Voltage (CLK+, CLK−)3 400 800 2000 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate4 1 GSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns 1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal. 2 Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C. 3 When using the PLL, a differential swing of 2 V p-p is recommended. 4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V. |
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