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CY8C20247-24LKXI Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY8C20247-24LKXI Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 43 page CY8C20xx7/S Document Number: 001-69257 Rev. *I Page 8 of 43 16-pin QFN (10 Sensing Inputs)[7] Table 2. Pin Definitions – CY8C20237, CY8C20247/S [8] Pin No. Type Name Description Figure 3. CY8C20237, CY8C20247/S Device Digital Analog 1 I/O I P2[5] Crystal output (XOut) 2 I/O I P2[3] Crystal input (XIn) 3 IOHR I P1[7] I2C SCL, SPI SS 4 IOHR I P1[5] I2C SDA, SPI MISO 5 IOHR I P1[3] SPI CLK 6 IOHR I P1[1] ISSP CLK[9], I2C SCL, SPI MOSI 7 Power VSS Ground connection 8 IOHR I P1[0] ISSP DATA[9], I2C SDA, SPI CLK[10] 9 IOHR I P1[2] Driven Shield Output (optional) 10 IOHR I P1[4] Optional external clock (EXTCLK) 11 Input XRES Active high external reset with internal pull-down 12 IOH I P0[4] 13 Power VDD Supply voltage 14 IOH I P0[7] 15 IOH I P0[3] Integrating input 16 IOH I P0[1] Integrating input LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. QFN (Top View) AI, XOut, P2[5] AI, I2 C SCL, SPI SS, P1[7] AI, I2 C SDA, SPI MISO, P1[5] 1 2 3 4 11 10 9 P0[4] , AI P1[2] , AI AI , XIn, P2[3] P1[4] , EXTCLK, AI XRES 12 Notes 7. No center pad. 8. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor. 9. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 10. Alternate SPI clock. |
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