CY8C20xx7/S

Document Number: 001-69257 Rev. *I

Page 11 of 43

32-pin QFN (25 Sensing Inputs)[18]

Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [19]

Pin

No.

Type

Name

Description

Digital

Analog

1

IOH

I

P0[1]

Integrating input

2

I/O

I

P2[5]

Crystal output (XOut)

3

I/O

I

P2[3]

Crystal input (XIn)

4

I/O

I

P2[1]

5

I/O

I

P4[3]

6

I/O

I

P3[3]

7

I/O

I

P3[1]

8

IOHR

I

P1[7]

9

IOHR

I

P1[5]

10

IOHR

I

P1[3]

SPI CLK.

11

IOHR

I

P1[1]

MOSI.

12

Power

Ground connection

13

IOHR

I

P1[0]

SPI CLK[21]

14

IOHR

I

P1[2]

Driven Shield Output (optional)

15

IOHR

I

P1[4]

Optional external clock input

(EXTCLK)

16

IOHR

I

P1[6]

17

Input

XRES Active high external reset with

internal pull-down

18

I/O

I

P3[0]

19

I/O

I

P3[2]

20

I/O

I

P4[0]

21

I/O

I

P4[2]

22

I/O

I

P2[0]

23

I/O

I

P2[2]

Driven Shield Output (optional)

24

I/O

I

P2[4]

Driven Shield Output (optional)

25

IOH

I

P0[0]

Driven Shield Output (optional)

26

IOH

I

P0[2]

Driven Shield Output (optional)

27

IOH

I

P0[4]

28

IOH

I

P0[6]

29

Power

30

IOH

I

P0[7]

31

IOH

I

P0[3]

Integrating input

32

Power

Ground connection

CP

Power

Center pad must be connected to

ground

LEGEND

A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

AI

,P0[1]

AI

,P2[5]

AI , XOut

,P2[3]

AI , XIn

,P2[1]

AI ,P4[3]

AI ,P3[3]

QFN

(Top View)

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

AI ,P3[1]

AI ,I2 C SCL, SPI SS,P1[7]

P2[4] ,AI

P2[2] ,AI

P3[0] ,AI

XRES

P2[0] ,AI

P4[2] ,AI

P4[0] ,AI

P3[2] ,AI

Notes

it must be electrically floated and not connected to any other signal.

20. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

alternate pins if you encounter issues.

21. Alternate SPI clock.