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CY8C20247S-24LKXIT Datasheet(PDF) 2 Page - Cypress Semiconductor |
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CY8C20247S-24LKXIT Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 43 page CY8C20xx7/S Document Number: 001-69257 Rev. *I Page 2 of 43 Logic Block Diagram CAPSENSE SYSTEM 1K/2 K SRAM Interrupt Controller Sleep and Watchdog Multiple Clock Sources Internal Low Speed Oscillator (ILO) 6/12/ 24 MHz Internal Main Oscillator (IMO) PSoC CORE CPU Core(M8C) Supervisory ROM (SROM) 8K/16K/32 K Flash Nonvolatile Memory SYSTEM RESOURCES SYSTEM BUS Analog Reference SYSTEM BUS Port 3 Port2 Port 1 Port 0 CapSense Module Global Analog Interconnect 1.8/2.5/3 V LDO Analog Mux I2C Slave SPI Master/ Slave POR and LVD System Resets Internal Voltage References Three 16- Bit Programmable Timers PWRSYS (Regulator) Port 4 Digital Clocks Comparator #2 Comparator #1 [2] Note 2. Internal voltage regulator for internal circuitry |
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