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CY14E101J2-SXI Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY14E101J2-SXI
Description  1-Mbit (128 K x 8) Serial (I2C) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14E101J2-SXI Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY14C101J
CY14B101J
CY14E101J
Document Number: 001-54050 Rev. *M
Page 8 of 31
Memory Control Register
The Memory Control Register contains the following bits:
BP1:BP0: Block Protect bits are used to protect 1/4, 1/2 or full
memory array. These bits can be written through a write
instruction to the 0x00 location of the Control Register Slave
device. However, any STORE cycle causes transfer of SRAM
data into a nonvolatile cell regardless of whether or not the
block is protected. The default value shipped from the factory
for BP0 and BP1 is ‘0’.
SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to
lock the serial number. Once the bit is set to ‘1’, the serial
number registers are locked and no modification is allowed.
This bit cannot be cleared to ‘0’. The serial number is secured
on the next STORE operation (Software STORE or AutoStore).
If AutoStore is not enabled, user must perform the Software
STORE operation to secure the lock bit status. If a STORE was
not performed, the serial number lock bit will not survive the
power cycle. The default value shipped from the factory for SNL
is ‘0’.
Command Register
The Command Register resides at address “AA” of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable and sleep mode operation as listed in
Table 5. Refer to Serial Number on page 16 for details on how to
execute a command register byte.
STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether a write has been performed
since the last NV operation. After the tSTORE cycle time is
completed, the SRAM is activated again for read and write
operations.
RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive the power
cycle. The part comes from the factory with AutoStore Enabled
and 0x00 written in all cells.
ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive power cycle.
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power-Up RECALL operation cannot be
disabled in any case.
SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM takes
tSS time to process the SLEEP request. Once the SLEEP
command is successfully registered and processed, the
nvSRAM toggles HSB LOW, performs a STORE operation to
secure the data to nonvolatile memory and then enters into
SLEEP mode. Whenever nvSRAM enters into sleep mode, it
initiates non volatile STORE cycle which results in losing an
endurance cycle per sleep command execution. A STORE
cycle starts only if a write to the SRAM has been performed
since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode as follows:
1. The Master sends a START command
2. The Master sends Control Registers Slave device ID with I2C
Write bit set (R/W = ‘0’)
3. The Slave (nvSRAM) sends an ACK back to the Master
4. The Master sends Command Register address (0xAA)
0xAA
Command
Register
Write only Allows commands for
STORE,
RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
Table 3. Memory Control Register Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0SNL
(0)
0
0
BP1
(0)
BP0
(0)
00
Table 4. Block Protection
Level
BP1:BP0
Block Protection
000
None
1/4
01
0x18000–0x1FFFF
1/2
10
0x10000–0x1FFFF
1
11
0x00000–0x1FFFF
Table 2. Control Registers Map (continued)
Address
Description Read/Write
Details
Table 5. Command Register Bytes
Data Byte
[7:0]
Command
Description
0011 1100
STORE
STORE SRAM data to nonvolatile
memory
0110 0000
RECALL
RECALL data from nonvolatile
memory to SRAM
0101 1001
ASENB
Enable AutoStore
0001 1001
ASDISB
Disable AutoStore
1011 1001
SLEEP
Enter Sleep Mode for low power
consumption


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