CY14V256LA

Document Number: 001-76295 Rev. *B

Page 10 of 22

AC Switching Characteristics

Over the Operating Range

Parameters [9]

Description

35 ns

Unit

Cypress

Parameters

Alt

Parameters

Min

Max

SRAM Read Cycle

Chip enable access time

–

35

ns

[10]

Read cycle time

35

–

ns

[11]

Address access time

–

35

ns

Output enable to data valid

–

15

ns

[11]

Output hold after address change

3

–

ns

[12, 13]

Chip enable to output active

3

–

ns

[12, 13]

Chip disable to output inactive

–

13

ns

[12, 13]

Output enable to output active

0

–

ns

[12, 13]

Output disable to output inactive

–

13

ns

[12]

Chip enable to power active

0

–

ns

[12]

Chip disable to power standby

–

35

ns

SRAM Write Cycle

Write cycle time

35

–

ns

Write pulse width

25

–

ns

Chip enable to end of write

25

–

ns

Data setup to end of write

12

–

ns

Data hold after end of write

0

–

ns

Address setup to end of write

25

–

ns

Address setup to start of write

0

–

ns

Address hold after end of write

0

–

ns

Write enable to output disable

–

13

ns

[12, 13]

Output active after end of write

3

–

ns

Notes

10. WE must be HIGH during SRAM read cycles.

11. Device is continuously selected with CE and OE LOW.

12. These parameters are guaranteed by design and are not tested.

13. Measured ±200 mV from steady state output voltage.

14. If WE is low when CE goes low, the outputs remain in the high-impedance state.