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CY14MB064J2A-SXIT Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY14MB064J2A-SXIT
Description  64-Kbit (8 K x 8) Serial (I2C) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14MB064J2A-SXIT Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY14MB064J1A/CY14MB064J2A
CY14ME064J1A/CY14ME064J2A
Document Number: 001-70393 Rev. *I
Page 10 of 28
address counter to this address. A following read operation will
start from the address 0x09 in this case also.
Note If the user tries to read/write access an address that does
not exist (for example 0x0D in Control Register Slave), nvSRAM
responds with a NACK immediately after the out-of-bound
address is transmitted. The address counter remains unchanged
and holds the previous successful read or write operation
address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
More details on write instruction are provided in the section,
Memory Slave Access on page 10
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
In case of the Control Register Slave, when a burst read is
performed such that it flows to a non-existent address, the reads
operation will loop back to 0x00. This is applicable, in particular
for the Command Register.
There are the following ways to end a read operation:
1. The Master issues a NACK on the 9th clock cycle followed by
a STOP or a Repeated START condition on the 10th clock
cycle.
2. Master generates a STOP or Repeated START condition on
the 9th clock cycle.
More details on write instruction are provided in Section Memory
Slave Access on page 10.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform Read or Write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x0000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after all the 8 data bits have
been received by the nvSRAM. The nvSRAM sends an ACK
signal after a successful write operation. A write operation may
be terminated by the master by generating a STOP condition or
a Repeated START operation. If the master desires to abort the
current write operation without altering the memory contents, this
should be done using a START/STOP condition prior to the 8th
data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and address counter will not
be incremented.
Figure 10. Single-Byte Write into nvSRAM (except Hs-mode)
S1
0
1
0
A2 A1 A0
0
A
A
A
A
S
T
A
R
T
S
T
0
P
P
Most Significant Address Byte
Least Significant Address Byte
Data Byte
Memory Slave Address
SDA Line
By Master
By nvSRAM
XX
X
Figure 11. Multi-Byte Write into nvSRAM (except Hs-mode)
S1
0
1
0
A2 A1 A0
0
A
A
A
A
S
T
A
R
T
Most Significant Address
Byte
Memory Slave Address
SDA Line
By Master
A
S
T
0
P
P
Data Byte N
By nvSRAM
XX
X
Least Significant Address
Byte
Data Byte 1


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