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CY62128ELL-45SXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62128ELL-45SXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 19 page  CY62128E MoBL® 1-Mbit (128 K × 8) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05485 Rev. *K Revised June 3, 2013 1-Mbit (128 K × 8) Static RAM Features ■ Very high speed: 45 ns ■ Temperature ranges ❐ Industrial: –40 °C to +85 °C ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ Voltage range: 4.5 V to 5.5 V ■ Pin compatible with CY62128B ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 4 A (Industrial) ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power down when deselected ■ complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and 32-pin thin small outline package (TSOP) Type I packages Functional Description The CY62128E is a high performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW) To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The CY62128E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 5 for more details and suggested alternatives. Logic Block Diagram A0 I/O0 I/O7 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 A1 A2 A3 A4 A5 A6 A7 A8 A9 POWER DOWN WE OE COLUMN DECODER 128K x 8 ARRAY INPUT BUFFER A10 A11 CE1 CE2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 |
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