Document Number: 001-13194 Rev. *G

Page 8 of 16

Switching Waveforms

Figure 4. Read Cycle 1 (Address Transition Controlled) [17, 18]

Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19, 20]

Figure 6. Write Cycle No. 1 (WE Controlled) [20, 21, 22, 23]

PREVIOUS DATA VALID

DATA VALID

RC

ADDRESS

DATA OUT

50%

50%

DATA VALID

HIGH IMPEDANCE

IMPEDANCE

HIGH

ADDRESS

CE

DATA OUT

SUPPLY

CURRENT

OE

DATA VALID

ADDRESS

CE

WE

DATA I/O

OE

NOTE 24

Notes

18. WE is HIGH for read cycle.

signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

24. During this period, the I/Os are in output state. Do not apply input signals.