Document Number: 38-05485 Rev. *K

Page 9 of 19

Switching Waveforms

Figure 6. Read Cycle 1 (Address Transition Controlled) [20, 21]

Figure 7. Read Cycle No. 2 (OE Controlled) [21, 22, 23]

Figure 8. Write Cycle No. 1 (WE Controlled) [23, 24, 25, 26]

PREVIOUS DATA VALID

DATA VALID

RC

ADDRESS

DATA OUT

50%

50%

DATA VALID

HIGH IMPEDANCE

IMPEDANCE

HIGH

ADDRESS

CE

DATA OUT

SUPPLY

CURRENT

OE

DATA VALID

ADDRESS

CE

WE

DATA I/O

OE

NOTE 27

Notes

21. WE is HIGH for read cycle.

terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

27. During this period, the I/Os are in output state and input signals must not be applied.