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CYF0018V33L-133BGXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CYF0018V33L-133BGXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 36 page CYF0018V CYF0036V CYF0072V Document Number: 001-53687 Rev. *M Page 11 of 36 Table 4. Writing and Reading Configuration Registers in Parallel Mode SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK Operation 10 0 1 First rising edge because both LD and WEN are low X X Parallel write to first register 10 0 1 Second rising edge X X Parallel write to second register 10 0 1 Third rising edge X X Parallel write to third register 10 0 1 Fourth rising edge X X Parallel write to fourth register 10 0 1 XX 10 0 1 XX 10 0 1 XX 10 0 1 Tenth rising edge X X Parallel write to tenth register 10 0 1 Eleventh rising edge X X Parallel write to first register (roll back) 10 1 0 X First rising edge since both LD and REN are low X Parallel read from first register 10 1 0 X Second rising edge X Parallel read from second register 10 1 0 X Third rising edge X Parallel read from third register 10 1 0 X Fourth rising edge X Parallel read from fourth register 10 1 0 X X 10 1 0 X X 10 1 0 X X 10 1 0 X Tenth rising edge X Parallel read from tenth register 10 1 0 X Eleventh rising edge X Parallel read from first register (roll back) 1 X 1 1 X X X No operation X1 0 X Rising edge X X Write to FIFO memory X1 X 0 X Rising edge X Read from FIFO memory 0 0 X 1 X X X Illegal operation |
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