DCP

(SE Waveform)

Idle

Link Off

Bus Phase

H

PD*

Active

DCN

(SE Waveform)

DC

(DIFF)

DDP

(SE Waveform)

DDN

(SE Waveform)

DD

(DIFF)

Idle

L

LM4308

SNLS225C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

OFF PHASE

In the OFF phase, differential transmitters are turned off and the lines are both driven to Ground. Figure 7 shows

the transition of the serial bus into the OFF phase. The link may be powered down by asserting Master and

Slave PD* pins, the Master PD* pin alone or stopping the clock . To avoid loss of data the clock input should only

be asserted after the serial bus has been in the IDLE state for at least 100 DC clock cycles. This also applies to

when Master’s PD* input is asserted. The 100 DC clock cycles give the Slave enough time to complete any write

operations received from the serial bus.

Do not asserted the Slave PD* pin alone, as this will not reset the link properly. If the Slave PD* pin is asserted,

the Master’s PD* must also be asserted to generate a proper start up sequence.

Figure 7. Serial Bus Power Down Timing

I80 CPU INTERFACE COMPATIBILITY

The CPU Interface mode provides compatibility between an i80 CPU Interface and a small form factor (SFF)

Display or other fixed I/O port application. Both WRITE and READ transactions are supported. READs require a

dual access on the Master to complete the operation.

10

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