FM25H20 - 2Mb SPI FRAM

Document Number: 001-85935 Rev. *A

Page 9 of 16

Endurance

The FM25H20 is capable of being accessed at least

10

14

times, reads or writes. An F-RAM memory

operates

with a read and restore

mechanism.

Therefore, an endurance cycle is applied on a row

basis for each access (read or write) to the memory

array. The F-RAM architecture is based on an array

of rows and columns. Rows are defined by A17-A3

and column addresses by A2-A0.

See Block

Diagram (pg 2) which shows the array as 32K rows

of 64-bits each. The entire row is internally accessed

each time a byte in that row is read or written. All 8

bytes in the row are counted separately for each

access in an endurance calculation. The table below

shows endurance calculations for 256-byte repeating

loop, which includes an op-code, a starting address (3

bytes), and a sequential 256-byte data stream. This

causes each byte to experience eight endurance

cycles through the loop. F-RAM read and write

endurance is very high even at 40MHz clock rate.

Table 5. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop

SCK Freq

(MHz)

Endurance

Cycles/sec.

Endurance

Cycles/year

Years to Reach

10

40

153,848

4.85 x 10

12

20.6

20

76,924

2.43 x 10

12

41.2

10

38,462

1.21 x 10

12

82.4

5

19,231

6.06 x 10

11

164.8