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TDA8034HN-C1,151 Datasheet(PDF) 7 Page - NXP Semiconductors |
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TDA8034HN-C1,151 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 30 page TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3.1. — 5 September 2011 7 of 30 NXP Semiconductors TDA8034HN Smart card interface 8.3 Clock circuits The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034HN automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. Automatic clock source detection is performed on each activation command (falling edge of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is checked during a time window defined by the internal oscillator. If a clock is detected, the internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator is started. When an external clock is used, it is mandatory that the clock is applied to pin XTAL1 before the falling edge of the signal on pin CMDVCCN. The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either fxtal, 1 2 fxtal or 1 4 fxtal or 1 8 fxtal as shown in Table 4. Remark: The levels on both pins must not be allowed to change simultaneously but should be separated by a minimum of 10 ns. The frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. In addition, only the first and last clock pulse around the change has the correct width. When dynamically changing the frequency, the modification is only effective after 10 clock periods on pin XTAL1. The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %. When the frequency of the clock signal on pin CLK is either fxtal, 12 fxtal, 14 fxtal or 1 8 fxtal, the frequency dividers guarantee a duty cycle between 45 % and 55 %. enclkin and clkxtal are internal signal names. Fig 5. Basic layout for using an external clock Table 4. Clock configuration Pin CLKDIV1 level Pin CLKDIV2 level Pin CLK frequency LOW LOW 1 8 fxtal LOW HIGH 1 4 fxtal HIGH HIGH 1 2 fxtal HIGH LOW fxtal 001aak992 DIGITAL MULTIPLEXER CRYSTAL XTAL1 XTAL2 clkxtal enclkin |
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