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BCM5464SA1KRBG Datasheet(PDF) 2 Page - Broadcom Corporation. |
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BCM5464SA1KRBG Datasheet(HTML) 2 Page - Broadcom Corporation. |
2 / 2 page O V ERVI EW ® Phone: 949-450-8700 Fax: 949-450-8710 E-mail: info@broadcom.com Web: www.broadcom.com BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 © 2003 by BROADCOM CORPORATION. All rights reserved. 5464S-PB07-R 12/10/03 Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/ or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners. The BCM5464S consists of four complete 10/100/1000BASE-T Gigabit Ethernet transceivers integrated on a single monolithic CMOS chip, and is a member of Broadcom’s QuadSquadTM family of quad Gigabit Ethernet PHYs. The BCM5464S is optimized for low-power and small footprint size to enable high port density applications. The BCM5464S enables a new class of cost effective Gigabit Ethernet equipment by lowering system cost and reducing power dissipation by nearly 25%, driving the delivery of Gigabit bandwidth to the desktop. The BCM5464S digital signal processor based architecture and advanced power management techniques combine to achieve robust and low-power operation over the existing Category 5 twisted-pair wiring. The BCM5464S architecture not only meets the requirements of IEEE’s 802.3, 802.3u, and 802.3ab, but maintains the industry’s highest level of margin over IEEE requirements for echo, NEXT, and FEXT. Low- power is key to implementing high-density Gigabit switches, and the BCM5464S has the lowest power in the industry at less than 750 mW per port. In addition, the BCM5464S has extremely low EMI emissions, which reduces the design constraints required to meet EMI radiation specifications. The BCM5464S supports GMII, RGMII, SGMII, and SerDes MAC interfaces. A unique feature of the BCM5464S is its ability to support both copper and fiber networks, with an integrated SerDes PHY interface that can connect directly to a fiber-optic module. Switching between copper and fiber media can be accomplished either automatically or through software control. The BCM5464S monitors copper link and fiber signal detect status, and automatically swaps either copper traffic or fiber traffic to the MAC/switch based on priorities set at initialization. This device is another member of Broadcom’s 0.13-µm Gigabit copper PHY family, joining the BCM5404, BCM5414, BCM5421, BCM5421S, BCM5424, and BCM5434. The 0.13-µm process is the optimal process that offers the best performance, lowest cost, and lowest power for Gigabit copper solutions. Devices based on the 0.13-µm process offer an excellent long term cost curve, enabling better cost reduction over time compared to older technologies without having to redesign or requalify a new part. Each port of the BCM5464S is fully independent and has individual interface, control and status registers, and incorporates a number of advanced features. A link quality indicator LED gives installers an instant visual indication if there are any problems with the wiring plant supporting operation at the preferred speed. This includes physical wiring defects that the BCM5464S cannot automatically correct for, channel conditions such as excessive cable length and return loss, crosstalk, echo, and noise. Broadcom’s cable analyzer software can be used with the device to provide remote management of the cable and a first level of diagnostics and fault isolation. The BCM5464S also has ESD tolerance well above typical industry standards. This prevents ESD damage not only during manufacturing but during CESD events in the field. The CESD is an ESD event that occurs when an electrically charged network cable is plugged into a network port, which is an issue becoming more prevalent with recent cable installations. The BCM5464 can tolerate over 4 kV of CESD. {1:4}* {1:2}* *{1:4} Refers to the four separate Gigabit transceivers in the BCM5464S {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* {1:4}* SGIN± SCLK± SGOUT± {1:4}* SGIN SGOUT TRD XTALI XTALO RDAC 16 TX DAC Gain Automatic Control PGA ADC Auto- Negotiation Clock Generator Bias Generator FFE Echo Cannceller XTALK Cannceller X3 DFE/ Trellis Decoder Timing & Phase Decoder MII Registers MII MGMT Control Symbol Encoder MUX MUX SERDES/ SGMII Symbol Decoder/ Aligner 2 2 2 2 2 2 2 2 16 16 TXD TX_EN TX_ER GTX_CLK TX_CLK COL CRS RX_CLK RX_DV RX_ER RXD[7:0] MDC MDIO NTR MODES |
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