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DS80000470H-page 3

PIC24FJ64GA004 FAMILY

RTCC

—

24.

Write errors to ALCFGRPT register.

X

Slave mode

25.

In Slave mode, ACKSTAT bit state change.

X

26.

Issues with write operations on I2CxSTAT.

X

UART

27.

IR baud clock only available during transmit.

X

I/O

PPS

28.

Issues with digital signal priorities with RP12

and RP18.

X

UART

UERIF

Interrupt

29.

No UERIF flag with multiple errors.

X

X

X

X

UART

FIFO Error

Flags

30.

PERR and FERR are not correctly set for all

bytes in receive FIFO.

XX

XX

Core

BOR

31.

Spontaneous BOR events with low-range

XX

XX

Core

Instruction

Set

32.

Loop count errors with REPEAT instruction

and R-A-W stalls.

X

Memory

PSV

33.

False address error traps at lower boundary

of PSV space.

XX

X

RTCC

—

34.

Decrement of alarm repeat counter under

certain conditions.

XX

X

SPI

Master

mode

35.

SPIF and SPIBEN may become set early

under certain conditions.

X

Master

mode

36.

Module may respond to its own master

transmission as a slave under certain

conditions.

XX

XX

Slave mode

37.

Failure to respond correctly to some

reserved addresses in 10-bit mode.

XX

XX

38.

TBF flag not cleared under certain

conditions.

X

UART

—

39.

Erroneous sampling and framing errors

when using two Stop bits.

XX

XX

Oscillator

SOSC

40.

Low-power SOSC unimplemented.

X

Voltage

Regulator

—

41.

Standby mode not available.

X

Core

Code-Protect

42.

General code protection disables

bootloader functionality.

X

SPIx

—

43.

Interrupts when SPIx is operating in

Enhanced Buffer mode.

XX

XX

UART

44.

mode

X

Core

Doze Mode

45.

Instruction execution glitches following

DOZE bit changes.

XX

XX

TABLE 2:

SILICON ISSUE SUMMARY (CONTINUED)

Module

Feature

Item

Number

Issue Summary

A3/A4

B4

B5

B8

Note 1:

Only those issues indicated in the last column apply to the current silicon revision.