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X28HC256DI-15 Datasheet(PDF) 2 Page - Rochester Electronics |
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X28HC256DI-15 Datasheet(HTML) 2 Page - Rochester Electronics |
2 / 21 page 1 ® FN8108.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC256 256k, 32k x 8-Bit 5V, Byte Alterable EEPROM The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years. Features • Access time: 70ns • Simple byte and page write - Single 5V supply - No external high voltages or VP-P control circuits - Self-timed - No erase before write - No complex programming algorithms - No overerase problem • Low power CMOS - Active: 60mA - Standby: 500µA • Software data protection - Protects data against system level inadvertent writes • High speed page write capability • Highly reliable Direct Write™ cell - Endurance: 1,000,000 cycles - Data retention: 100 years • Early end of write detection - DATA polling - Toggle bit polling • Pb-free plus anneal available (RoHS compliant) Block Diagram X BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHES Y BUFFERS LATCHES AND DECODER CONTROL LOGIC AND TIMING 256kBIT EEPROM ARRAY I/O0 TO I/O7 DATA INPUTS/OUTPUTS CE OE VCC VSS A0 TO A14 WE ADDRESS INPUTS Data Sheet May 7, 2007 |
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