8XC196KC/8XC196KC20

PIN DESCRIPTIONS

Symbol

Name and Function

Main supply voltage (5V).

portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D

and Port 0 to function.

ANGND

Reference ground for the A/D converter. Must be held at nominally the same potential as

Timing pin for the return from powerdown circuit. This pin also supplies the programming

voltage on the EPROM device.

XTAL1

Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

CLKOUT

Output of the internal clock generator. The frequency of CLKOUT is

the oscillator

frequency.

RESET

Reset input and open drain output.

BUSWIDTH

Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus

cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an

8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.

NMI

A positive transition causes a vector through 203EH.

INST

Output high during an external memory read indicates the read is an instruction fetch. INST

is valid throughout the bus cycle. INST is activated only during external memory accesses

and output low for a data fetch.

EA

Input for memory select (External Access). EA equal high causes memory accesses to

locations 2000H through 5FFFH to be directed to on-chip ROM/E PROM. EA equal to low

causes accesses to those locations to be directed to off-chip memory. Also used to enter

programming mode.

ALE/ADV

Address Latch Enable or Address Valid output, as selected by CCR. Both pin options

provide a signal to demultiplex the address from the address/data bus. When the pin is

ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during

external memory accesses.

RD

Read signal output to external memory. RD is activated only during external memory reads.

WR/WRL

Write and Write Low output to external memory, as selected by the CCR. WR will go low for

every external write, while WRL will go low only for external writes where an even byte is

being written. WR/WRL is activated only during external memory writes.

BHE/WRH

Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will

go low for external writes to the high byte of the data bus. WRH will go low for external

writes where an odd byte is being written. BHE/WRH is activated only during external

memory writes.

READY

Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,

or for bus sharing. When the external memory is not being used, READY has no effect.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.

Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,

HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

Port 0

8-bit high impedance input-only port. These pins can be used as digital inputs and/or as

analog inputs to the on-chip A/D converter.

Port 1

8-bit quasi-bidirectional I/O port.

Port 2

8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.

Pins 2.6 and 2.7 are quasi-bidirectional.

7