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X28HC256FM-90 Datasheet(PDF) 10 Page - Rochester Electronics |
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X28HC256FM-90 Datasheet(HTML) 10 Page - Rochester Electronics |
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10 / 21 page  9 FN8108.2 May 7, 2007 Resetting Software Data Protection In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. SYSTEM CONSIDERATIONS Because the X28HC256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. CE WE STANDARD OPERATING MODE VCC DATA ADDRESS AAA 5555 55 2AAA 80 5555 tWC AA 5555 55 2AAA 20 5555 FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 20 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 AFTER tWC, RE-ENTERS UNPROTECTED STATE FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE X28HC256 |
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