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56

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D22

D23

D24

GND

D25

D26

D27

LVDSGND

A0M

A0P

A1M

A1P

LVDSGND

A2M

A2P

CLKINM

CLKINP

A3M

A3P

LVDSGND

PLLGND

PLLGND

SHTDN

CLKOUT

D0

GND

D21

D20

D19

GND

D18

D17

D16

D15

D14

D13

GND

D12

D11

D10

D9

D8

D7

GND

D6

D5

D4

D3

D2

D1

DGG PACKAGE

(TOP VIEW)

SN75LVDS82

www.ti.com

SLLS259I

– NOVEMBER 1996 – REVISED APRIL 2011

FlatLink

™ RECEIVER

Check for Samples: SN75LVDS82

1

FEATURES

23

•

4:28 Data Channel Expansion at up to

238 Mbytes/s Throughput

•

Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

•

Four Data Channels and Clock Low-Voltage

Differential Channels In and 28 Data and

Clock Low-Voltage TTL Channels Out

•

Operates From a Single 3.3-V Supply With

250 mW (Typ)

•

5-V Tolerant SHTDN Input

•

Falling Clock-Edge-Triggered Outputs

•

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal Pitch

•

Consumes Less Than 1 mW When Disabled

•

Wide Phase-Lock Input Frequency

Range . . . 31 MHz to 68 MHz

•

No External Components Required for PLL

•

Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

•

Improved Replacement for the

National

™ DS90C582

DESCRIPTION

The SN75LVDS82 FlatLink

™ receiver contains four

serial-in, 7-bit parallel-out shift registers, a 7

× clock

synthesizer, and five low-voltage differential signaling

(LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,

over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL)

synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or

SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7

×)

the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.

A phase-locked loop (PLL) clock synthesizer circuit generates a 7

× clock for internal clocking and an output clock

for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

FlatLink is a trademark of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright

© 1996–2011, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.