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A8293SESTR-T Datasheet(PDF) 10 Page - Allegro MicroSystems |
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A8293SESTR-T Datasheet(HTML) 10 Page - Allegro MicroSystems |
10 / 19 page Single LNB Supply and Control Voltage Regulator A8293 10 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Control Registers (I2C™-Compatible Write Register) All main functions of the A8293 are controlled through the I2C™- compatible interface via the 8-bit Control registers. As the A8293 contains numerous control options, it is necessary to have two control registers. Each register contains up to 6 bits of data (bit 0 to bit 5), followed by 2 bits for the register address (bit 6 and bit 7). The power-up states for the control functions are all 0s. The following tables define the control bits for each address and the settings for output voltage: Table 1. Control Register Address (I1, I0) = 00 Bit Name Function 0 VSEL0 See table 3, Output Voltage Amplitude Selection 1 VSEL1 2 VSEL2 3 VSEL3 0: LNB = Low range 1: LNB = High range 4 ODT 1 (recommended): The ODT functions are always enabled, but setting 1 recommended at all times. 5 ENB 0: Disable LNB Output 1: Enable LNB Output 6 I0 Address Bit: 0 7 I1 Address Bit: 0 Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output. Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage levels are defined in table 3, Output Voltage Amplitude Selection. Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output. 0 selects the low level voltage and 1 selects the high level. The low-level center voltage is 12.709 V nominal and the high level is 18.042 V nominal. These may be increased in steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits. Bit 4 ODT The overcurrent disable timer is always enabled. Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled. Bit 6 I0 Address Bit 7 I1 Address |
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