10-Bit Serial Input Latched Source Driver

A6810

5

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TIMING REQUIREMENTS and SPECIFICATIONS

Serial Data present at the input is transferred to the shift

register on the logic “0” to logic “1” transition of the CLOCK

input pulse. On succeeding CLOCK pulses, the registers shift

data information towards the SERIAL DATA OUTPUT. The

SERIAL DATA must appear at the input prior to the rising edge

of the CLOCK input waveform.

Information present at any register is transferred to the

respective latch when the STROBE is high (serial-to-parallel

conversion). The latches will continue to accept new data as

long as the STROBE is held high. Applications where the

latches are bypassed (STROBE tied high) will require that the

BLANKING input be high during serial data entry.

When the BLANKING input is high, the output source

drivers are disabled (OFF); the PNP active pull-down sink

drivers are ON. The information stored in the latches is not

affected by the BLANKING input. With the BLANKING input

low, the outputs are controlled by the state of their respective

latches.

BLANKING

OUT

N

Dwg. WP-030A

DATA

10%

50%

en(BQ)

t

dis(BQ)

t

HIGH = ALL OUTPUTS BLANKED (DISABLED)

r

t

f

t

50%

90%

A.

Data Active Time Before Clock Pulse

B.

Data Active Time After Clock Pulse

C.

D.

E.

NOTE – Timing is representative of a 10 MHz clock. Higher

speeds may be attainable; operation at high temperatures will

reduce the specified maximum clock frequency.

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

OUT

N

Dwg. WP-029

50%

SERIAL

DATA OUT

DATA

DATA

10%

90%

50%

50%

50%

C

A

B

D

E

LOW = ALL OUTPUTS ENABLED

p(STH-QL)

t

p(CH-SQX)

t

DATA

p(STH-QH)

t