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MCP6S26-ISL Datasheet(PDF) 7 Page - Microchip Technology |
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MCP6S26-ISL Datasheet(HTML) 7 Page - Microchip Technology |
7 / 42 page 2003-2012 Microchip Technology Inc. DS21117B-page 7 MCP6S21/2/6/8 1.1 DC Output Voltage Specs / Model 1.1.1 IDEAL MODEL The ideal PGA output voltage (VOUT) is: EQUATION (see Figure 1-7). This equation holds when there are no gain or offset errors and when the VREF pin is tied to a low impedance source (<< 0.1 ) at ground potential (VSS = 0V). 1.1.2 LINEAR MODEL The PGA’s linear region of operation, including offset and gain errors, is modeled by the line VO_linear, shown in Figure 1-7. EQUATION The endpoints of this line are at VO_ideal =0.3V and VDD-0.3V. The gain and offset specifications referred to in the electrical specifications are related to Figure 1-7, as follows: EQUATION FIGURE 1-7: Output Voltage Model with the standard condition VREF = VSS = 0V. 1.1.3 OUTPUT NON-LINEARITY Figure 1-8 shows the Integral Non-Linearity (INL) of the output voltage. EQUATION The output non-linearity specification in the electrical specifications is related to Figure 1-8 by: EQUATION FIGURE 1-8: Output Voltage INL with the standard condition VREF = VSS = 0V. V O_ideal GV IN = V REF V SS 0V == where: G is the nominal gain V O_linear G1 g E + V IN 0.3V V OS + – 0.3V + = V REF V SS 0V == g E 100% V 2 V 1 – GV DD 0.6V – -------------------------------------- = V OS V 1 G1 g E + ------------------------- = GT A g E T A ---------- = G+1 = 0 0 0.3 VDD-0.3 VDD VOUT (V) VIN (V) 0.3 VDD - 0.3 VDD G GG V1 V2 INL V OUT V O_linear – = V ONL max V 4 V3 V DD 0.6V – --------------------------------- = 0 V3 V4 INL (V) VIN (V) 0.3 VDD - 0.3 VDD G GG 0 |
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