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CY7C63723-SC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C63723-SC Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 49 page  CY7C63722 CY7C63723 CY7C63743 FOR FOR Document #: 38-08022 Rev. *B Page 9 of 49 USB Device Address 0x10 R/W USB Device Address register 14-1 EP0 Counter Register 0x11 R/W USB Endpoint 0 counter register 14-4 EP0 Mode Register 0x12 R/W USB Endpoint 0 configuration register 14-2 EP1 Counter Register 0x13 R/W USB Endpoint 1 counter register 14-4 EP1 Mode Register 0x14 R/W USB Endpoint 1 configuration register 14-3 EP2 Counter Register 0x15 R/W USB Endpoint 2 counter register 14-4 EP2 Mode Register 0x16 R/W USB Endpoint 2 configuration register 14-3 USB Status & Control 0x1F R/W USB status and control register 13-1 Global Interrupt Enable 0x20 R/W Global interrupt enable register 21-1 Endpoint Interrupt Enable 0x21 R/W USB endpoint interrupt enables 21-2 Timer (LSB) 0x24 R Lower 8 bits of free-running timer (1 MHz) 18-1 Timer (MSB) 0x25 R Upper 4 bits of free-running timer 18-2 WDR Clear 0x26 W Watchdog Reset clear - Capture Timer A Rising 0x40 R Rising edge Capture Timer A data register 19-2 Capture Timer A Falling 0x41 R Falling edge Capture Timer A data register 19-3 Capture Timer B Rising 0x42 R Rising edge Capture Timer B data register 19-4 Capture Timer B Falling 0x43 R Falling edge Capture Timer B data register 19-5 Capture TImer Configuration 0x44 R/W Capture Timer configuration register 19-7 Capture Timer Status 0x45 R Capture Timer status register 19-6 SPI Data 0x60 R/W SPI read and write data register 17-2 SPI Control 0x61 R/W SPI status and control register 17-3 Clock Configuration 0xF8 R/W Internal / External Clock configuration register 9-2 Processor Status & Control 0xFF R/W Processor status and control 20-1 Table 8-1. I/O Register Summary (continued) Register Name I/O Address Read/Write Function Fig. |
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Similar Description - CY7C63723-SC |
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