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CY7C63743-QXC Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY7C63743-QXC Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 49 page CY7C63722 CY7C63723 CY7C63743 FOR FOR Document #: 38-08022 Rev. *B Page 11 of 49 before the part executes code. See Section 10.1 for more details. 1 = Disables the LVR circuit. 0 = Enables the LVR circuit. Bit 2: Precision USB Clocking Enable The Precision USB Clocking Enable only affects operation in internal oscillator mode. In that mode, this bit must be set to 1 to cause the internal clock to automatically pre- cisely tune to USB timing requirements (6 MHz ±1.5%). The frequency may have a looser initial tolerance at pow- er-up, but all USB transmissions from the chip will meet the USB specification. 1 = Enabled. The internal clock accuracy is 6 MHz ±1.5% after USB traffic is received. 0 = Disabled. The internal clock accuracy is 6 MHz ±5%. Bit 1: Internal Clock Output Disable The Internal Clock Output Disable is used to keep the inter- nal clock from driving out to the XTALOUT pin. This bit has no effect in the external oscillator mode. 1 = Disable internal clock output. XTALOUT pin will drive HIGH. 0 = Enable the internal clock output. The internal clock is driven out to the XTALOUT pin. Bit 0: External Oscillator Enable At power-up, the chip operates from the internal clock by default. Setting the External Oscillator Enable bit HIGH dis- ables the internal clock, and halts the part while the external resonator/crystal oscillator is started. Clearing this bit has no immediate effect, although the state of this bit is used when waking out of suspend mode to select between inter- nal and external clock. In internal clock mode, XTALIN pin will be configured as an input with a weak pull-down and can be used as a GPIO input (P2.1). 1 = Enable the external oscillator. The clock is switched to external clock mode, as described in Section 9.1. 0 = Enable the internal oscillator. 9.1 Internal/External Oscillator Operation The internal oscillator provides an operating clock, factory set to a nominal frequency of 6 MHz. This clock requires no external components. At power-up, the chip operates from the internal clock. In this mode, the internal clock is buffered and driven to the XTALOUT pin by default, and the state of the XTALIN pin can be read at Port 2.1. While the internal clock is enabled, its output can be disabled at the XTALOUT pin by setting the Internal Clock Output Disable bit of the Clock Configuration Register. Setting the External Oscillator Enable bit of the Clock Config- uration Register HIGH disables the internal clock, and halts the part while the external resonator/crystal oscillator is started. The steps involved in switching from Internal to External Clock mode are as follows: 1. At reset, chip begins operation using the internal clock. 2. Firmware sets Bit 0 of the Clock Configuration Register. For example, mov A, 1h ; Set Bit 0 HIGH (External Oscil- lator Enable bit). Bit 7 cleared gives faster start-up iowr F8h ; Write to Clock Configuration Register 3. Internal clocking is halted, the internal oscillator is disabled, and the external clock oscillator is enabled. 4. After the external clock becomes stable, chip clocks are re-enabled using the external clock signal. (Note that the time for the external clock to become stable depends on the external resonating device; see next section.) 5. After an additional delay the CPU is released to run. This delay depends on the state of the Ext. Clock Resume Delay bit of the Clock Configuration Register. The time is 128 µs if the bit is 0, or 4 ms if the bit is 1. 6. Once the chip has been set to external oscillator, it can only return to internal clock when waking from suspend mode. Clearing bit 0 of the Clock Configuration Register will not re-enable internal clock mode until suspend mode is entered. See Section 11.0 for more details on suspend mode operation. If the Internal Clock is enabled, the XTALIN pin can serve as a general purpose input, and its state can be read at Port 2, Bit 1 (P2.1). Refer to Figure 12-8 for the Port 2 Data Register. In this mode, there is a weak pull-down at the XTALIN pin. This input cannot provide an interrupt source to the CPU. 9.2 External Oscillator The user can connect a low-cost ceramic resonator or an external oscillator to the XTALIN/XTALOUT pins to provide a precise reference frequency for the chip clock, as shown in Figure 9-1. The external components required are a ceramic resonator or crystal and any associated capacitors. To run from the external resonator, the External Oscillator Enable bit of the Clock Configuration Register must be set to 1, as explained in the previous section. Start-up times for the external oscillator depend on the resonating device. Ceramic resonator based oscillators typically start in less than 100 µs, while crystal based oscil- lators take longer, typically 1 to 10 ms. Board capacitance should be minimized on the XTALIN and XTALOUT pins by keeping the traces as short as possible. An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. 10.0 Reset The USB Controller supports three types of resets. The effects of the reset are listed below. The reset types are: 1. Low-voltage Reset (LVR) 2. Brown Out Reset (BOR) 3. Watchdog Reset (WDR) The occurrence of a reset is recorded in the Processor Status and Control Register (Figure 20-1). Bits 4 (Low-voltage or Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to record the occurrence of LVR/BOR and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. |
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