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MCP2120-ISL Datasheet(PDF) 7 Page - Microchip Technology |
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MCP2120-ISL Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 36 page  © 2007 Microchip Technology Inc. DS21618B-page 7 MCP2120 2.5 Modulation When the UART receives data to be transmitted, the data needs to be modulated. This modulated signal drives the IR transceiver module. Figure 2-2 shows the encoding of the modulated signal. Each bit time is comprised of 16-bit clocks. If the value to be transmitted (as determined by the TX pin) is a logic low, then the TXIR pin will output a low level for 7-bit clock cycles, a logic high level for 3-bit clock cycles, and then the remaining 6-bit clock cycles will be low. If the value to transmit is a logic high, then the TXIR pin will output a low level for the entire 16-bit clock cycles. 2.6 Demodulation The modulated signal from the IR transceiver module needs to be demodulated to form the received data. As demodulation occurs, the bit value is placed on the RX pin in UART format. Figure 2-3 shows the decoding of the modulated signal. Each bit time is comprised of 16 bit clocks. If the value to be received is a logic low, then the RXIR pin will be a low level for the first 3-bit clock cycles, and then the remaining 13-bit clock cycles will be high. If the value to be received is a logic high, then the RXIR pin will be a high level for the entire 16-bit clock cycles. The level on the RX pin will be in the appropriate state for the entire 16 clock cycles. FIGURE 2-2: Encoding FIGURE 2-3: Decoding BITCLK TX TXIR 01 0 0 0 1 16 CLK Start Bit Data bit 0 Data bit 1 Data bit 2 Data bit... 7 CLK 12 Tosc BITCLK RX RXIR 01 0 0 0 1 ≥ 1.6 µs 13 CLK (or ≤ 50.5 µs typical) 16 CLK 16 CLK 16 CLK 16 CLK 16 CLK 16 CLK 16 CLK 8 CLK Start Bit Data bit 0 Data bit 1 Data bit 2 Data bit ... (CLK) |
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