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ADS62P28 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS62P28 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 65 page  ADS62P19 SLAS937 – APRIL 2013 www.ti.com TIMING REQUIREMENTS: LVDS AND CMOS MODES (1) (continued) Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock, 1.5-VPP clock amplitude, CLOAD = 5 pF (2), and R LOAD = 100 Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.7 V to 1.9 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARALLEL CMOS MODE(7) (At fS = 210 MSPS) tSTART Input clock to data delay Input clock falling edge crossover to start of data valid(8) 2.5 ns tDV Data valid time Time interval of valid data(8) 1.7 2.7 ns tPDI Input clock falling edge crossover to output clock rising edge tPDI = 0.28 × tS + tdelay crossover Clock propagation delay 100 MSPS ≤ sampling frequency ≤ 150 MSPS tdelay 5.5 7.0 8.5 ns tS = 1 / sampling frequency Output clock duty cycle , CLKOUT Output clock duty cycle 43% 100 MSPS ≤ sampling frequency ≤ 150 MSPS Rise time measured from 20% to 80% of DRVDD tRISE, Data rise time, Fall time measured from 80% to 20% of DRVDD 1.2 ns tFALL Data fall time 1 ≤ sampling frequency ≤ 210 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time, Fall time measured from 80% to 20% of DRVDD 0.8 ns tCLKFALL Output clock fall time 1 ≤ sampling frequency ≤ 150 MSPS Output buffer enable (OE) tOE Time to valid data after output buffer becomes active 100 ns to data delay(9) (7) For fS > 150 MSPS, TI recommends using an external clock for data capture instead of the device output clock signal (CLKOUT). (8) Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V. (9) The output buffer enable is controlled by serial interface register 40h. The output buffer becomes active when serial control data for the output buffer are latched on the 16th SCLK falling edge when SEN is low. Table 2. LVDS Timings at Lower Sampling Frequencies SETUP TIME (ns) HOLD TIME (ns) tPDI (ns) SAMPLING FREQUENCY (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX 210 0.75 1.1 0.75 1.15 7.5 9 10.5 185 0.9 1.25 0.85 1.25 7.9 9.4 10.9 153 1.15 1.55 1.1 1.5 8.7 10.2 11.7 125 1.6 2 1.45 1.85 9.7 11.2 12.7 < 80 2 2 (enable low-speed mode for fS ≤ 80) (1) 1 ≤ fS ≤ 80 12.6 (enable low-speed mode for fS ≤ 80) (1) (1) Low-speed mode can only be enabled with the serial interface configuration. Table 3. CMOS Timings at Lower Sampling Frequencies with Respect to Input Clock TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK SAMPLING FREQUENCY (MSPS) tSTART (ns) DATA VALID TIME (ns) MIN TYP MAX MIN TYP MAX 210 2.5 1.7 2.7 190 1.9 2 3 170 0.9 2.7 3.7 150 6 3.6 4.6 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS62P19 |
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