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TPS3420DDRYT Datasheet(PDF) 11 Page - Texas Instruments |
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TPS3420DDRYT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 19 page trst No Second Pulse PB1 PB2 RST ttimer trst ttimer ttimer TPS3420 TPS3421 TPS3422 www.ti.com SBVS211A – AUGUST 2012 – REVISED MARCH 2013 PUSH-BUTTON TIMER SELECTION (TS) The TPS342x offer two different push-button timer options (ttimer) for system flexibility with the use of TS pin. Connect the TS pin to either GND or VCC for two different timing options, as shown in Table 1. Table 1. Push-Button Timer Option Examples PUSH-BUTTON TIMER PRODUCT TS = VCC TS = GND RESET PULSE TPS3420DDRYR/T 12.5 s 7.5 s N/A TPS3421EGDRYR/T 0 s 7.5 s 400 ms TPS3422EGDRYR/T 0 s 7.5 s 400 ms During normal operation, the TS pin state should not be changed because TS is intended to be permanently connected to either ground or VCC. The state of the TS pin is checked during power-up and when either PBx input is high. Therefore, if a different timing option is desired, the state must be changed during power-off, or when either PBx input is high, in order to avoid false operation. OUTPUT (RST) The TPS342x have an open-drain output. A pull-up resistor must be used to hold the line high when the output is in a high-impedance state (not asserted). By connecting a pull-up resistor to the proper voltage rail, the output can be connected to other devices at correct interface voltage levels. The TPS342x output can be pulled up to 6.5 V, independent of the device supply voltage. To ensure proper voltage levels, make sure to choose the correct pull-up resistor values. The pull-up resistor value is determined by VOL, sink current capability, and output leakage current (Ilkg(OD)). These values are specified in the Electrical Charactersitcs table. The Inputs (PB1, PB2) section describes how the output is asserted or deasserted. See Figure 1 (TPS3420), Figure 2 (TPS3421) , or Figure 3 (TPS3422) for a timing diagram that describes the relationship between the PB1 and PB2 inputs and the output. Figure 17 shows the TPS3421 reset timing. Figure 17. TPS3421 Reset Timing Diagram Any change in input condition is detected after reset is deasserted. If input PB1 or PB2 has a pulse (low-to-high- to-low) during the trst period, the change is not recognized by the device. If input PB1 or PB2 go high during the trst period, the change is detected after reset is deasserted. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS3420 TPS3421 TPS3422 |
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