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ADS5295IPFP Datasheet(PDF) 7 Page - Texas Instruments |
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ADS5295IPFP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 91 page  ADS5295 www.ti.com SBAS595 – DECEMBER 2012 TIMING REQUIREMENTS (1) Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine-wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7 V to 1.9 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tA Aperture delay 4 ns Aperture delay matching Between any two channels of the same device ±200 ps Between two devices at the same temperature and Variation of aperture delay ±1 ns LVDD supply tJ Aperture jitter Sample uncertainty 320 fs rms Time to valid data after coming out of standby 5 µs Wake-up time Time to valid data after coming out of global power- 100 µs down mode One-wire LVDS Output interface 12 Clock cycles ADC latency(2) Two-wire LVDS Output interface 16 Clock cycles TWO-WIRE, 12x SERIALIZATION tSU Data setup time Data valid to zero-crossing of LCLKP 0.52 ns tH Data hold time Zero-crossing of LCLKP to data becoming invalid 0.62 ns tPDI = Input clock rising edge crossover to output clock (11/12) tPDI Clock propagation delay ns rising edge crossover × tS + tDELAY tDELAY Delay time 8.5 11 13.5 ns Duty cycle of differential clock LVDS bit clock duty cycle 50 % (LCLKP – LCLKN) ACROSS ALL SERIALIZATION MODES Rise time measured from –100 mV to +100 mV, tFALL Data fall time 0.11 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tRISE Data rise time 0.11 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tCLKRISE Output clock rise time 0.11 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tCLKFALL Output clock fall time 0.11 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS (1) Timing parameters are ensured by design and characterization, but are not tested in production. (2) At higher frequencies, tPDI is greater than one clock period and the overall latency = ADC latency + 1. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS5295 |
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