IDT5V41065

2 OUTPUT PCIE GEN1/2 SYNTHESIZER

IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER

8

IDT5V41065

REV E 112111

AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1

Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85

° C

Note 2: Measurement taken from a single-ended waveform.

Note 3: Measurement taken from a differential waveform.

Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.

Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.

Electrical Characteristics - Differential Phase Jitter

Note 1. Guaranteed by design and characterization, not 100% tested in production.

Note 2. See http://www.pcisig.com for complete specs.

Note 3: Applies to 100MHz, spread off and 0.5% down spread only.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

25

MHz

Output Frequency

HCSL termination

25

200

MHz

LVDS termination

25

100

MHz

HCSL

850

mV

HCSL

-150

mV

Absolute

250

550

mV

Variation over all edges

140

mV

100

ps

Frequency Synthesis Error

All outputs

0

ppm

Modulation Frequency

Spread spectrum

30

32.9

33

kHz

From 0.175 V to 0.525 V

175

700

ps

From 0.525 V to 0.175 V

175

700

ps

125

ps

Output to Output Skew

50

ps

45

55

%

All outputs

50

100

ns

All outputs

50

100

ns

Stabilization Time

From power-up VDD=3.3 V

1.8

ms

Spread Spectrum Transition

Time

Stabilization time after spread

spectrum changes

730

ms

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

Jitter, Phase

PCIe Gen1

32

86

ps (p-p)

1,2,3

PCIe Gen2, 10 kHz < f < 1.5 MHz

0.8

3

ps (RMS)

1,2,3

2.3

3.1

ps (RMS)

1,2,3