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MPC9600AE Datasheet(PDF) 11 Page - Integrated Device Technology |
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MPC9600AE Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 15 page MPC9600 REVISION 6 JANUARY 7, 2013 11 ©2013 Integrated Device Technology, Inc. MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER At the load end the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Figure 9. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. Figure 10. Optimized Dual Line Termination The following figures illustrate the measurement reference for the MPC9600 clock driver circuit. Figure 11. CCLK MPC9600 AC Test Reference Figure 12. PCLK MPC9600 AC Test Reference OutB tD = 3.9386 OutA tD = 3.8956 In 2 4 6 8 10 12 14 Time (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 ZO = 50 ZO = 50 14 MPC9600 Output Buffer RS = 22 RS = 22 14 + 22 || 22 = 50 || 50 25 = 25 Pulse Generator Z = 50 RT = 50 ZO = 50 RT = 50 ZO = 50 MPC9600 DUT VTT VTT Differential Pulse Generator Z = 50 RT = 50 ZO = 50 RT = 50 ZO = 50 MPC9600 DUT VTT VTT |
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