MPC962305 REVISION 8 JANUARY 8, 2013

5

©2013 Integrated Device Technology, Inc.

MPC962305 Data Sheet

LOW-COST, 3.3V ZERO DELAY BUFFEr

APPLICATIONS INFORMATION

Figure 2. Static Phase Offset Test Reference

Figure 3. Output Duty Cycle (DC)

Figure 4. Device-to-Device Skew

Figure 5. Cycle-to-Cycle Jitter

Figure 6. Output Transition Time Test Reference

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

1.4 V

GND

1.4 V

GND

GND

GND

CCLK

FB_IN

The time from the PLL controlled edge to the non-controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

1.4 V

GND

GND

GND

DEVICE 1

DEVICE 2

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

2.0

0.8