6

COMMERCIALTEMPERATURERANGE

IDT72V70180 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 128 x 128

Connection Memory

10000001

10000010

Data Memory

0

0

0

0

1

1

1

0

2

1

1

3

Stream

Control Register

5716 drw03

10000000

The Control Register is only accessed when A7-A0

are all zeroed. When A7 =1, up to 32 bytes are

randomly accessable via A0-A4 at any one instant.

Of which stream these bytes (channels) are accessed

is determined by the state of CRb1 -CRb0.

0

1

10011111

External Address Bits A7-A0

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 31

Channel 31

Channel 31

Channel 31

Figure 3. Addressing Internal Memories

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., RX n channel m data comes from the

TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For

proper per-channel loopback operation, the contents of the frame delay offset

registers must be set to zero.

INITIALIZATION OF THE IDT72V70180

After power up, the state of the connection memory is unknown. As such,

theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe

ODE is low, the microprocessor can initialize the device, program the active

paths, and disable unused outputs by programming the OE bit in connection

memory. Once the device is configured, the ODE pin (or OSB bit depending

on initialization) can be switched.

CONNECTION MEMORY CONTROL

If the ODE pin or the OSB bit is high, the OE bit of each connection memory

location controls the output drivers-enables (if high) or disables (if low). See

Table 4 for detail.

Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween

Processor Mode and Connection Mode. If high, the contents of the connection

memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and

the channel address bit (CAB) of the connection memory defines the source

information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput

from data memory.

The

V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation

allows the per-channel selection between variable and constant throughput

delay modes.