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LT8697EUDD Datasheet(PDF) 9 Page - Linear Dimensions Semiconductor |
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LT8697EUDD Datasheet(HTML) 9 Page - Linear Dimensions Semiconductor |
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9 / 28 page  LT8697 9 8697p For more information www.linear.com/LT8697 pin FuncTions VIN (Pins 5, 6): The VIN pins supply current to the LT8697 internal circuitry and to the internal topside power switch. These pins must be tied together and be locally bypassed. Place the positive terminal of the input capacitor as close as possible to the VIN pins, and the negative terminal as close as possible to the PGND pins. PGND (Pins 7, 8): Power Switch Ground. These pins are the return path of the internal bottom side power switch and must be tied together. Place the negative terminal of the input capacitor as close as possible to the PGND pins. NC (Pins 9-12): No Connect. These pins are floating and are not connected to the LT8697. Tie these pins to the same copper as the exposed pad. See Figure 8. SW (Pins 13, 14, 15): The SW pins are the outputs of the internal power switches. Tie these pins together and con- nect them to the inductor and boost capacitor. This node should be kept small on the PCB for good performance. BST (Pin 16): This pin is used to provide a drive voltage, higher than the input voltage, to the topside power switch. Place a 0.1µF boost capacitor between this pin and SW as close as possible to the LT8697 IC. INTVCC (Pin 17): Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are powered from this voltage. The INTVCC maximum output current is 20mA. INTVCC current will be supplied from SYS if VSYS > 3.1V, otherwise current will be drawn from VIN. Decouple this pin to power ground with at least a 1µF low ESR ceramic capacitor. Do not load the INTVCC pin with external circuitry. SYS (Pin 18): The internal regulator will draw current from SYS instead of VIN when SYS is tied to a voltage higher than 3.3V. The SYS pin must be tied to the side of the inductor opposite the SW pin and must be bypassed by the output capacitor. SYS is also the secondary input to the error amp and regulates to a maximum of 5.8V. PG (Pin 19): The PG pin is the open-drain output of an internal window comparator. PG remains low until the USB5V pin is within ±9% of the final regulation voltage and there are no fault conditions. The PG transition delay is approximately 40µs. PG is valid when VIN is above 3.4V regardless of the EN/UV state. USB5V (Pin 20): The LT8697 regulates the USB5V pin to 5V. For cable drop compensation, the USB5V pin input current is proportional to the sensed output current. The USB5V ESD cell clamps to 9V. To allow the LT8697 output to survive a short to 30V, the 10k RCDC resistor must be in place between the USB5V pin and the output to limit the current into this pin. ISP(Pin21):CurrentSense(+)Pin.Thisisthenon-inverting input to the current sense amplifier. ISN (Pin 22): Current Sense (–) Pin. This is the inverting input to the current sense amplifier. RCBL (Pin 23): Cable Drop Compensation Program Pin. A resistor RCBL tied from RCBL to ground programs cable drop compensation by setting the USB5V input current. RCBL can source 1mA. Excessive capacitive loading on RCBL can degrade load transient response. Isolate load capacitance on this pin by tying a 100k resistor between RCBL and the capacitive load. The RCBL load monitor output is valid when the LT8697 is enabled, otherwise the output is zero. Float RCBL if neither the current monitor nor the cable drop compensation feature is desired. ICTRL (PIN 24): Current Adjustment Pin. ICTRL adjusts the maximum VISP – VISN drop before the LT8697 limits the output current. Connect directly to INTVCC or float for a full scale VISP – VISN threshold of 48mV or apply values between ground and 1V to modulate the output current limit. There is an internal 2µA pull-up current on this pin. Float or tie to INTVCC when unused. GND (Exposed Pad Pin 25): Ground. The exposed pad must be connected to the negative terminal of the input capacitor and soldered to the PCB for proper operation and in order to lower the thermal resistance. |
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