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BR25S256FVM-WE2 Datasheet(PDF) 11 Page - Rohm |
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BR25S256FVM-WE2 Datasheet(HTML) 11 Page - Rohm |
11 / 19 page Technical Note 11/18 BR25S□□□ Series www.rohm.com 2010.12 - Rev.B © 2010 ROHM Co., Ltd. All rights reserved. ●Method to cancel each command ○READ, RDSR ・Method to cancel : cancel by CSB = “H”. ○WRITE、PAGE WRITE a:Ope code or address input area Cancellation is available by CSB=”H”. b:Data input area (D7~D1 input area) Cancellation is available by CSB=”H”. c:Data input area (D0 area) In this area, cancellation is not available. When CSB is set HIGH, write starts. d:tE/W area In the area c, by rising CSB, write starts. While writing, by any input, cancellation cannot be made. Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more. ○WRSR a:From ope code to 15-th clock rise Cancellation is available by CSB=”H”. b:From 15-th clock rise to 16-th clock rise (write enable area) In this area, cancellation is not available. When CSB is set HIGH, write starts. c:After 16-th clock rise. Cancellation is available by CSB=”H”. However, if write starts (CSB is rised) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more. ○WREN/WRDI a:From ope code to 7-th clock rise, cancellation is available by CSB = “H”. b:Cancellation is not available 7-th clock. Fig.40 READ cancel valid timing Fig.41 RDSR cancel valid timing Fig.44 WREN/WRDI cancel valid timing Ope code Address a Data tE/W b d c 8bits 8bits 16bits D7 b D6 D5 D4 D3 D2 D1 D0 SCK SI c Fig.43 WRSR cancel valid timing Ope code Address Cancel available in all areas of read mode Data 8 bits 8 bits 16 bits Ope code Cancel available in all areas of rdsr mode Data 8 bits 8 bits Ope code Data tE/W 8 bits 14 15 16 17 D1 D0 a b c 8 bits a b c SCK SI Ope code 8 bits 6 7 8 a b SCK Fig.42 WRITE cancel valid timing |
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