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NCP561SN18T1G Datasheet(PDF) 7 Page - ON Semiconductor

Part # NCP561SN18T1G
Description  150 mA CMOS Low Iq Low-Dropout Voltage Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP561SN18T1G Datasheet(HTML) 7 Page - ON Semiconductor

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NCP561
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7
APPLICATIONS INFORMATION
A typical application circuit for the NCP561 series is
shown in Figure 13.
Input Decoupling (C1)
A 1.0
mF capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP561
package. Higher values and lower ESR will improve the
overall line transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Output Decoupling (C2)
The NCP561 is a stable Regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few m
W up to 3.0 W can thus safely be used.
The minimum decoupling value is 1.0
mF and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger values improve noise rejection and
load regulation transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K,
or C3216X7R1C105K
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to VIN.
Hints
Please be sure the VIN and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads a short as
possible.
Thermal
As power across the NCP561 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP561 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is
given by:
PD
+
TJ(max) *TA
R
qJA
If junction temperature is not allowed above the
maximum 125
°C, then the NCP561 can dissipate up to
400 mW @ 25
°C.
The power dissipated by the NCP561 can be calculated
from the following equation:
Ptot + [Vin *Ignd (Iout)] ) [Vin * Vout] *Iout
or
VINMAX +
PTOT ) VOUT * IOUT
IGND ) IOUT
If a 150 mA output current is needed then the ground
current from the data sheet is 4.0
mA. For an
NCP561SN30T1 (3.0 V), the maximum input voltage will
then be 5.6 V.
Figure 13. Typical Application Circuit
VOUT
Battery or
Unregulated
Voltage
C1
C2
OFF
ON
1
2
3
5
4
+
+


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