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CY7C028V-20AI Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C028V-20AI Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 24 page CY7C027V/027AV/028V CY7C037AV/038V Document Number: 38-06078 Rev. *G Page 8 of 24 Data Retention Mode The CY7C027V/027AV/028V and CY7037AV/038V are de- signed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power up and power down transitions 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 V) AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% 3ns 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 590 3.3 V OUTPUT R2 = 435 C= 30 pF VTH = 1.4 V OUTPUT C= 30 pF (b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2) R1 = 590 R2 = 435 3.3 V OUTPUT C= 5pF RTH = 250 including scope and jig) (Used for tLZ, tHZ, tHZWE, & tLZWE Timing Parameter Test Conditions [12] Max Unit ICCDR1 At VCCDR = 2 V 50 A Data Retention Mode 3.0 V 3.0 V VCC 2.0 V VCC to VCC – 0.2 V VCC CE tRC V IH Note 12. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested. |
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