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KSZ8721BL Datasheet(PDF) 6 Page - Micrel Semiconductor |
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KSZ8721BL Datasheet(HTML) 6 Page - Micrel Semiconductor |
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6 / 33 page  KS8721BL/SL Micrel M9999-051704 6 May 2004 Pin Description Pin Number Pin Name Type(1) Pin Function 1 MDIO I/O Management Independent Interface (MII) Data I/O. This pin requires an external 10K pull-up resistor. 2 MDC I MII Clock Input. This pin is synchronous to the MDIO. 3 RXD3/ Ipd/O MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. PHYAD When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping Options” section for details. 4 RXD2/ Ipd/O MII Receive Data Output. PHYAD2 During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping Options” section for details. 5 RXD1/ Ipd/O MII Receive Data Output. PHYAD3 During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See “Strapping Options” section for details. 6 RXD0/ Ipd/O MII Receive Data Output. PHYAD4 During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See “Strapping Options” section for details. 7 VDDIO P Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See “Circuit Design Ref. for Power Supply" section for details. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output. CRSDV/ During reset, the pull-up/pull-down value is latched as PCS_LPBK. See PCS_LPBK “Strapping Options” section for details. 10 RXC O MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output. During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See “Strapping Options” section for details. 12 GND GND Ground. 13 VDDC P Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section for details. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ I/O MII Transmit Clock Output. REFCLK Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock interface, pull up XI to VDDPLL 2.5V via 10k Ω resistor and leave XO pin unconnected. 16 TXEN Ipd MII Transmit Enable Input. 17 TXD0 Ipd MII Transmit Data Input. 18 TXD1 Ipd MII Transmit Data Input. Notes: 1. P = Power supply. GND = Ground. I = Input. I/O = Bidirectional. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu = Input w/ internal pull-up. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. O = Output. |
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