MT41J128M16HA-15ED datasheet(6/211 Pages) MICRON

Part #	MT41J128M16HA-15ED

Description	DDR3 SDRAM MT41J512M4 ??64 Meg x 4 x 8 Banks MT41J256M8 ??32 Meg x 8 x 8 Banks MT41J128M16 ??16 Meg x 16 x 8 Banks

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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List of Figures

Figure 1: DDR3 Part Numbers .......................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................. 11

Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14

Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15

Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15

Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16

Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17

Figure 8: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................... 22

Figure 9: 78-Ball FBGA – x4, x8 (HX) ............................................................................................................... 23

Figure 10: 96-Ball FBGA – x16 (HA) ................................................................................................................. 24

Figure 11: 96-Ball FBGA – x16 (JT) .................................................................................................................. 25

Figure 12: Thermal Measurement Point ......................................................................................................... 29

Figure 13: Input Signal .................................................................................................................................. 46

Figure 14: Overshoot ..................................................................................................................................... 47

Figure 15: Undershoot ................................................................................................................................... 47

Figure 16: VIX for Differential Signals .............................................................................................................. 49

Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 49

Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 50

Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 52

Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 53

Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 54

Figure 22: ODT Timing Reference Load .......................................................................................................... 57

Figure 23: tAON and tAOF Definitions ............................................................................................................ 58

Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 58

Figure 25: tADC Definition ............................................................................................................................. 59

Figure 26: Output Driver ................................................................................................................................ 60

Figure 27: DQ Output Signal .......................................................................................................................... 67

Figure 28: Differential Output Signal .............................................................................................................. 68

Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 68

Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 69

Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 70

Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 100

Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 101

Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 102

Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 103

Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 109

Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 110

Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 111

Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 112

Figure 40: Refresh Mode ............................................................................................................................... 119

Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 121

Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 122

Figure 43: DLL Disable tDQSCK .................................................................................................................... 123

Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 125

Figure 45: Write Leveling Concept ................................................................................................................. 126

Figure 46: Write Leveling Sequence ............................................................................................................... 129

Figure 47: Write Leveling Exit Procedure ....................................................................................................... 130

Figure 48: Initialization Sequence ................................................................................................................. 132

Figure 49: MRS to MRS Command Timing (tMRD) ......................................................................................... 133

Figure 50: MRS to nonMRS Command Timing (tMOD) .................................................................................. 134

2Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT41J128M16HA-15ED Datasheet(PDF) 6 Page - Micron Technology

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