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871002AGI-02LF Datasheet(PDF) 9 Page - Integrated Device Technology

Part # 871002AGI-02LF
Description  Differential-to-0.7V HCSL Differential PCI EXPRESS??Jitter Attenuator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

871002AGI-02LF Datasheet(HTML) 9 Page - Integrated Device Technology

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ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
ICS871002AGI-02 REVISION A APRIL 14, 2010
9
©2010 Integrated Device Technology, Inc.
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and
other differential signals. The differential signal must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter HSTL drivers. If you are
using an HSTL driver from another vendor, use their termination
recommendation.
3A. CLK/nCLK Input Driven by an
IDT Open Emitter HSTL Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
R1
50
R2
50
1.8V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
HSTL
IDT
HSTL Driver
Differential
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
3.3V
LVPECL
Differential
Input
HCSL
*R3
33
*R4
33
CLK
nCLK
3.3V
3.3V
Zo = 50
Zo = 50
Differential
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Zo = 50
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120


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