DATA SHEET

ICS871002AGI-02 REVISION A APRIL 14, 2010

1

©2010 Integrated Device Technology, Inc.

Differential-to-0.7V HCSL Differential

PCI EXPRESS™ Jitter Attenuator

ICS871002I-02

General Description

The ICS871002I-02 is a high performance Jitter

Attenuator designed for use in PCI Express™systems.

In some PCI Express systems, such as those found in

desktop PCs, the PCI Express clocks are generated

from a low bandwidth, high phase noise PLL frequency

synthesizer. In these systems, a jitter attenuator may be required to

attenuate high frequency random and deterministic jitter components

from the PLL synthesizer and from the system board. The

ICS871002I-02 has two PLL bandwidth modes: 350kHz and

2200kHz. The 350kHz mode provides the maximum jitter

attenuation, but it also results in higher PLL tracking time. In this

mode, the spread spectrum modulation may also be attenuated. The

2200kHz bandwidth provides the best tracking skew and will pass

most spread profiles, but the jitter attenuation will not be as good as

the lower bandwidth modes. The ICS871002I-02 can be set for

different modes using the F_SELx pins as shown in Table 3C.

technology to achieve the lowest possible phase noise. The

device is packaged in a small 20 Lead TSSOP package, making it

ideal for use in space constrained applications such as PCI Express

add-in cards.

Features

LVPECL, LVDS, HSTL, HCSL, SSTL

attenuation/tracking skew design trade-offs

packages

PLL Bandwidth (typical) Table

HiPerClockS™

ICS

BW_SEL

0 = PLL Bandwidth: ~350kHz (default)

1 = PLL Bandwidth: ~2200kHz

÷5 (fixed)

VCO

490 - 640 MHz

Phase

Detector

Output Divider

00 ÷5

01 ÷4

10 ÷2 (default)

11 ÷1

Q0

nQ0

Q1

nQ1

FB_OUT

nFB_OU

BW_SEL

CLK

nCLK

FB_IN

nFB_IN

F_SEL[1:0]

MR

OE

Pulldown

Pullup:Pulldown

Pulldown

Pullup

Pullup

Pulldown

Pullup

Pulldown

2

IREF

0 = 350kHz

1 = 2200kHz

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

F_SEL0

F_SEL1

BW_SEL

MR

nFB_OUT

FB_OUT

IREF

nQ0

Q0

Q1

nQ1

nFB_IN

FB_IN

GND

nCLK

CLK

OE

Pin Assignment

ICS871002I-02

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm

package body

G Package

Top View

Block Diagram