Advanced Clock Drivers Device Data

2

Freescale Semiconductor

MC88LV926

Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View)

Description of the RST_IN/RST_OUT(LOCK)

Functionality (continued)

After the system start-up is complete and the 88LV926 is

phase-locked to the SYNC input signal (RST_OUT high), the

processor reset functionality can be utilized. When the

RST_IN pin is toggled low (min. pulse width=10 nS),

RST_OUT(LOCK) will go to the low state and remain there

for 1024 cycles of the ‘Q' output frequency (512 SYNC

cycles). During the time in which the RST_OUT(LOCK) is

actively pulled low, all the 88LV926 clock outputs will continue

operating correctly and in a locked condition to the SYNC

input (clock signals to the 68030/040/060 family of

processors must continue while the processor is in reset). A

propagation delay after the 1024th cycle RST_OUT(LOCK)

goes back to the high impedance state to be pulled high by

the resistor.

Power Supply Ramp Rate Restriction for Correct 030/040

Processor Reset Operation During System Start-up

Because the RST_OUT(LOCK) pin is an indicator of

phase-lock to the reference source, some constraints must

be placed on the power supply ramp rate to make sure the

RST_OUT(LOCK) signal holds the processor in reset during

system start-up (power-up). With the recommended loop filter

The phase-lock loop will begin attempting to lock to a

PLL could lock to the reference source, causing

RST_OUT(LOCK) to go high before the 88LV926 and 030/

040 processor is fully powered up, violating the processor

reset specification. Therefore, if it is necessary for the

rate must be less than 10 mS for proper 68030/040/060 reset

operation.

This ramp rate restriction can be ignored if the RST_IN pin

can be held low during system start-up (which holds

RST_OUT low). The RST_OUT(LOCK) pin will then be pulled

back high 1024 cycles after the RST_IN pin goes high.

19

20

18

17

16

15

14

13

12

11

2

1

3

4

5

6

7

8

9

10

GND

Q3

2X_Q

QCLKEN

MR

RST_IN

Q2

GND

RC1

RST_OUT(LOCK)

GND(AN)

PLL_EN

SYNC

Q1

GND

Q0

Table 1. Capacitance and Power Specifications

Symbol

Parameter

Value Type

Unit

Test Conditions

Input Capacitance

pF

Power Dissipation Capacitance

pF

Power Dissipation at 33MHz With 50

Ω

Thevenin Termination

90mW/Device

mW

T = 25

°C

Power Dissipation at 33MHz With 50

Ω

Parallel Termination to GND

225mW/Device

mW

T = 25

°C

MC88LV926

Low Skew CMOS PLL 68060 Clock Driver

NETCOM

IDT™ Low Skew CMOS PLL 68060 Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC88LV926

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