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PEB3264FV1.4 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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PEB3264FV1.4 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 374 page  DuSLIC Table of Contents Page Preliminary Data Sheet 10 DS3, 2003-07-11 6.1.3 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 6.1.4 Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . . 336 6.1.5 Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . . 338 6.1.6 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . 339 6.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 6.3 DuSLIC Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4 DuSLIC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4.1 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4.2 MCLK/FSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 6.4.3 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 6.4.3.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 6.4.3.2 Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 6.4.4 Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 6.4.5 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 6.4.5.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 6.4.5.2 Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 7 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 7.1 Internal Ringing (Balanced/Unbalanced) . . . . . . . . . . . . . . . . . . . . . . . . . 352 7.1.1 Circuit Diagrams Internal Ringing (Balanced & Unbalanced) . . . . . . . 353 7.1.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 7.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P . . . . . . . . . . 356 7.2.1 Circuit Diagrams External Unbalanced Ringing . . . . . . . . . . . . . . . . . . 357 7.3 DuSLIC Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 9 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 10 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 |
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