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SN74LVC1G74DQER Datasheet(PDF) 1 Page - Texas Instruments

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Part # SN74LVC1G74DQER
Description  Available in the Texas Instruments NanoFree??Package
Download  21 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74LVC1G74DQER Datasheet(HTML) 1 Page - Texas Instruments

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DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(TOP VIEW)
CLK
1
8
V
CC
CLK
1
8
VCC
CLK A1 1 8 A2 VCC
D
2
7
PRE
D
2
7
PRE
Q
3
6
CLR
D
Q
GND
B1
2 7 B2
C1
3 6 C2
D1
4 5 D2
PRE
CLR
Q
Q
3
6
CLR
GND
4
5
Q
GND
4
5
Q
See mechanical drawings for dimensions.
DQE PACKAGE
(TOP VIEW)
CLK
1 8
V
CC
D
Q
GND
2
7
3
6
4 5
PRE
CLR
Q
RSE PACKAGE
(TOP VIEW)
CLK
1
8
V
CC
D
Q
GND
2
7
3
6
4
5
PRE
CLR
Q
SN74LVC1G74
www.ti.com
SCES794C – SEPTEMBER 2009 – REVISED NOVEMBER 2012
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
Check for Samples: SN74LVC1G74
1
FEATURES
2
Available in the Texas Instruments NanoFree™
Ioff Supports Live Insertion, Partial Power
Package
Down Mode, and Back Drive Protection
Supports 5-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Inputs Accept Voltages to 5.5 V
ESD Protection Exceeds JESD 22
Max tpd of 5.9 ns at 3.3 V
2000-V Human-Body Model (A114-A)
Low Power Consumption, 10-
μA Max ICC
200-V Machine Model (A115-A)
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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