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RT8064ZQW Datasheet(PDF) 11 Page - Richtek Technology Corporation |
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RT8064ZQW Datasheet(HTML) 11 Page - Richtek Technology Corporation |
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11 / 13 page  RT8064 11 DS8064-07 November 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 3. Derating Curve of Maximum Power Dissipation Layout Considerations Follow the PCB layout guidelines for optimal performance of the IC. Connect the terminal of the input capacitor (s), CIN, as close to the VIN pin as possible. This capacitor provides the AC current into the internal power MOSFETs. LX node experiences high frequency voltage swings so should be kept within a small area. Keep all sensitive small signal nodes away from the LX node to prevent stray capacitive noise pick up. Connect the FB pin directly to the feedback resistors. The resistive voltage divider must be connected between VOUT and GND. Figure 4. PCB Layout Guide COMP SS EN VIN PGOOD FB LX RT GND 2 3 4 5 6 7 8 9 Place the compensation components as close to the IC as possible VOUT GND R2 R1 VIN CIN COUT VOUT L1 RCOMP CCOMP LX should be connected to inductor by wide and short trace, and keep sensitive components away from this trace Place the feedback resistors as close to the IC as possible Place the input and output capacitors as close to the IC as possible GND ROSC GND CSS Place the compensation components as close to the IC as possible VOUT GND R2 R1 VIN CIN COUT VOUT L1 RCOMP CCOMP LX should be connected to inductor by wide and short trace, and keep sensitive components away from this trace Place the feedback resistors as close to the IC as possible Place the input and output capacitors as close to the IC as possible GND ROSC COMP SS VIN PGOOD FB RT LX EN 7 6 5 1 2 3 4 8 9 GND CSS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 25 50 75 100 125 Ambient Temperature (°C) Four-Layer PCB SOP-8 (Exposed Pad) WDFN-8L 3x3 maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJAis the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125 °C. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25 °C can be calculated by the following formulas : PD(MAX) = (125 °C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) package PD(MAX) = (125 °C − 25°C) / (70°C/W) = 1.429W for WDFN-8L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, θJA. The derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. |
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