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EP2C20F256C8N Datasheet(PDF) 6 Page - Altera Corporation |
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EP2C20F256C8N Datasheet(HTML) 6 Page - Altera Corporation |
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6 / 470 page  vi Altera Corporation Cyclone II Device Handbook, Volume 1 Contents clkena signals .................................................................................................................................. 7–29 Board Layout ........................................................................................................................................ 7–30 VCCA & GNDA ............................................................................................................................. 7–31 VCCD & GND ................................................................................................................................. 7–33 Conclusion ............................................................................................................................................ 7–33 Section III. Memory Revision History .................................................................................................................................... 7–1 Chapter 8. Cyclone II Memory Blocks Introduction ............................................................................................................................................ 8–1 Overview ................................................................................................................................................. 8–1 Control Signals .................................................................................................................................. 8–3 Parity Bit Support ............................................................................................................................. 8–4 Byte Enable Support ........................................................................................................................ 8–4 Packed Mode Support ..................................................................................................................... 8–6 Address Clock Enable ...................................................................................................................... 8–6 Memory Modes ...................................................................................................................................... 8–8 Single-Port Mode .............................................................................................................................. 8–9 Simple Dual-Port Mode ................................................................................................................. 8–10 True Dual-Port Mode ..................................................................................................................... 8–12 Shift Register Mode ........................................................................................................................ 8–14 ROM Mode ...................................................................................................................................... 8–16 FIFO Buffer Mode ........................................................................................................................... 8–16 Clock Modes ......................................................................................................................................... 8–16 Independent Clock Mode .............................................................................................................. 8–17 Input/Output Clock Mode ........................................................................................................... 8–19 Read/Write Clock Mode ............................................................................................................... 8–22 Single-Clock Mode ......................................................................................................................... 8–24 Power-Up Conditions & Memory Initialization ........................................................................ 8–27 Read-During- Write Operation at the Same Address .................................................................... 8–28 Same-Port Read-During-Write Mode .......................................................................................... 8–28 Mixed-Port Read-During-Write Mode ........................................................................................ 8–29 Conclusion ............................................................................................................................................ 8–30 Referenced Documents ....................................................................................................................... 8–30 Chapter 9. External Memory Interfaces Introduction ............................................................................................................................................ 9–1 External Memory Interface Standards ................................................................................................ 9–2 DDR & DDR2 SDRAM .................................................................................................................... 9–2 QDRII SRAM ..................................................................................................................................... 9–5 Cyclone II DDR Memory Support Overview .................................................................................... 9–9 Data & Data Strobe Pins ................................................................................................................ 9–10 Clock, Command & Address Pins ............................................................................................... 9–14 Parity, DM & ECC Pins ................................................................................................................. 9–14 |
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