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EP2C20F256C8N Datasheet(PDF) 3 Page - Altera Corporation |
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EP2C20F256C8N Datasheet(HTML) 3 Page - Altera Corporation |
3 / 470 page Altera Corporation iii Contents Chapter Revision Dates ........................................................................... xi About This Handbook ............................................................................ xiii How to Contact Altera .......................................................................................................................... xiii Typographic Conventions .................................................................................................................... xiii Section I. Cyclone II Device Family Data Sheet Revision History .................................................................................................................................... 1–1 Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Low-Cost Embedded Processing Solutions .................................................................................. 1–1 Low-Cost DSP Solutions ................................................................................................................. 1–1 Features ................................................................................................................................................... 1–2 Referenced Documents ......................................................................................................................... 1–9 Document Revision History ................................................................................................................. 1–9 Chapter 2. Cyclone II Architecture Functional Description .......................................................................................................................... 2–1 Logic Elements ....................................................................................................................................... 2–2 LE Operating Modes ........................................................................................................................ 2–4 Logic Array Blocks ................................................................................................................................ 2–7 LAB Interconnects ............................................................................................................................ 2–8 LAB Control Signals ......................................................................................................................... 2–8 MultiTrack Interconnect ..................................................................................................................... 2–10 Row Interconnects .......................................................................................................................... 2–10 Column Interconnects .................................................................................................................... 2–12 Device Routing ............................................................................................................................... 2–15 Global Clock Network & Phase-Locked Loops ............................................................................... 2–16 Dedicated Clock Pins ..................................................................................................................... 2–20 Dual-Purpose Clock Pins .............................................................................................................. 2–20 Global Clock Network ................................................................................................................... 2–21 Global Clock Network Distribution ............................................................................................ 2–23 PLLs .................................................................................................................................................. 2–25 Embedded Memory ............................................................................................................................. 2–27 Memory Modes ............................................................................................................................... 2–30 Clock Modes .................................................................................................................................... 2–31 M4K Routing Interface .................................................................................................................. 2–31 |
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