4

Figure 4. Recommended Circuit Schematic for dc Coupling (at +5 V) between Optical Transceiver and Physical Layer IC

MOUNTING POST

NO INTERNAL CONNECTION

HFBR/HFCT-5208M

TOP VIEW

V

EER

RD

RD

SD

V

CCR

V

CCT

TD

TD

V

EET

1

234

567

8

9

C2

L1

L2

R2

R3

R1

R4

C5

C3

C4

R9

R10

V

AT V

TRANSCEIVER

R5

R7

R6

R8

C6

RD

RD

SD

V

CC

TD

TD

TERMINATION

AT PHY

DEVICE

INPUTS

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR PECL

SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE PECL SIGNALS.

RECOMMEND MULTI-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP OR

STRIPLINE SIGNAL PATHS BE USED.

R1 = R4 = R6 = R8 = R10 = 130 OHMS.

R2 = R3 = R5 = R7 = R9 = 82 OHMS.

C1 = C2 = C3 = C5 = C6 = 0.1 F.

C4 = C7 = 10 F.

L1 = L2 = 1 H COIL OR FERRITE

INDUCTOR (see text comments).

TERMINATION

AT TRANSCEIVER

INPUTS

Rx

Rx

Tx

Tx

V

CC

V

CC

C1

C7

MOUNTING POST

NO INTERNAL CONNECTION

Recommended Circuit Schematic

When designing the HFBR/HFCT-5208M circuit interface,

there are a few fundamental guidelines to follow. For

example, in the Recommended Circuit Schematic, Figure

4, the differential data lines should be treated as 50 ohm

Microstrip or stripline transmission lines. This will help to

minimize the parasitic inductance and capacitance effects.

Proper termination of the differential data signal will prevent

reflections and ringing which would compromise the signal

fidelity and generate unwanted electrical noise. Locate

termination at the received signal end of the transmission

line. The length of these lines should be kept short and of

equal length to prevent pulse-width distortion from

occurring. For the high-speed signal lines, differential signals

should be used, not single-ended signals. These differential

signals need to be loaded symmetrically to prevent

unbalanced currents from flowing which will cause

distortion in the signal.

In addition to these recommenda-tions, Avago

Technolgies’ Application Engineering staff is available for

consulting on best layout practices with various vendors’

serializer/deserializer, clock recovery/generation integrated

circuits.

Reference Design

Avago Technolgies has developed a reference design for

multimode and single-mode OC-12 ATM-SONET/SDH

applications shown in Figure 6. This reference design uses

a Vitesse Semiconductor Inc.’s VSC8117 clock recovery/

clock generation/serializer/deserializer integrated circuit and

a PMC-Sierra Inc. PM5355 framer IC. Application Note 1178

documents the design, layout, testing and performance of

this reference design. Gerber files, schematic and

application note are available from the Avago Technolgies

web site at the URL of http://www.avagotech.com